05 / 08 · What we check

Reset structure that behaves the same in sim and silicon.

Mixed synchronous and asynchronous resets, or resets that aren't properly released, are a classic source of designs that pass simulation but fail on the bench. We check your reset tree end to end.

01
Sync vs. async consistency. One reset strategy applied consistently, not mixed ad-hoc across modules.
02
Reset release timing. Asynchronous assertion with synchronous de-assertion to avoid recovery/removal violations.
03
Reset domain crossings. Reset signals synchronized correctly when they cross clock domains.
04
Power-up state. Registers that need a defined value at power-up actually have one.
05
Reset fan-out. Reset trees that won't create their own timing or loading problems.

Sample findingReset Analysis

process(clk, rst_n)
begin
  if rst_n = '0' then
    state <= IDLE;      -- async assert
  elsif rising_edge(clk) then
    state <= next_state; -- no sync de-assertion stage
  end if;
end process;

Asynchronous reset released without a synchronizerMajor

Without synchronizing the de-assertion edge, this reset risks recovery/removal timing violations at the flop.

Why it matters

What this check protects you from.

Deterministic power-up

A clean reset tree means your design starts in the same state every time, in sim and in silicon.

Fewer intermittent failures

Recovery/removal violations show up as rare, hard-to-reproduce glitches in the field.

Simpler STA

A consistent reset strategy is far easier to constrain correctly in your timing analysis.

All categories

Every review covers all 8.

Reset Analysis is one of eight categories in every FPGAStudio review. Explore the rest below.

Resource Optimization

DSP & Fixed-Point

Detailed Report

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