Service 04 / RTL Verification

Coverage you can put in front of a sign-off review.

Self-checking unit-level testbenches, directed and randomized stimulus, and assertions driven to a coverage target you choose. We take your design to 80% or 90% code coverage with functional and assertion coverage closed alongside it, and hand you a regression suite your own engineers can read and extend.

Get a free unit testbench → What we measure

Free unit testbench at 70% coverage, then from $6,500 →

Code coverage Functional coverage Assertion coverage Unit-level testbenches Formal verification CI regressions

coverage / sign-offEnterprise target

Line coverage100%

Branch coverage100%

FSM state & transition100%

Functional coverage100%

Assertion coverage100%

unreachable code waived with written justification

What we measure

Three kinds of coverage, because one is never enough.

Code coverage tells you the testbench executed your RTL. It does not tell you the design is correct. Closing all three together is what makes a coverage number mean something.

Coverage 01

Code coverage

Did the stimulus actually reach every part of the RTL? Measured across line, branch, condition, toggle, and FSM state and transition coverage.

Line Branch Condition Toggle FSM

Coverage 02

Functional coverage

Did the stimulus hit the scenarios that matter? Covergroups and crosses built from your specification, not inferred from the code, so gaps in the design show up as gaps in coverage.

Covergroups Coverpoints Crosses

Coverage 03

Assertion coverage

Are the properties that define correct behavior both written and exercised? SystemVerilog assertions checked in simulation and, where it pays, proven formally.

SVA Cover properties Formal proofs

Pricing

Start free, then pay by coverage target.

Send us one unit and we will build the testbench, write the test cases, and take it to 70% coverage at no cost, so you can judge the work before committing to a full engagement. Everything above that is priced by the coverage target you need to reach.

Unit Level

Free

One unit or module, up to 500 lines

Testbench built for your unit
Test cases delivered with it
70% code coverage
One per customer, no card required

Get your free unit testbench

Coverage 80%

From $6,500

Per unit or module, up to 2,000 lines

Everything in Unit Level
Unit-level testbenches and a written plan
80% code coverage
Functional coverage closed
Regression suite handed over

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Coverage 90%

Up to 5,000 lines of code

Everything in Coverage 80%
90% code coverage
Assertion coverage closed
Exclusions justified in writing
CI integration included

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Enterprise

Larger designs, sign-off support

Custom scope and turnaround
100% coverage where required
Formal property verification
Gate-level simulation
Team meeting with your expert
Dedicated NDA & onboarding

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What we deliver

A testbench your team can run, extend, and defend.

01
Verification plan. A written plan mapping every requirement to the coverage points that prove it, so coverage is traceable to the specification rather than to whatever the testbench happened to hit.
02
Unit-level testbenches. One self-checking bench per module, in plain SystemVerilog or VHDL. No class libraries, no factory, no phasing. An engineer on your team can open it, read it top to bottom, and extend it without learning a methodology first.
03
Directed and randomized stimulus. Directed tests for the cases you already know matter, plus randomized vectors with constraints to reach the corners nobody thought to write a test for.
04
Assertions. SystemVerilog assertions capturing protocol and interface rules, so violations are caught at the source instead of three modules downstream.
05
Coverage closure. The gap between your target and reality worked down deliberately, with every unreachable item excluded in writing and justified.
06
Regression suite and CI hookup. The whole thing wired into your pipeline so coverage is measured on every commit rather than once before tape-out.

Sample deliverableCoverage & assertions

// Functional coverage: are the cases we care about hit?
covergroup axi_burst_cg @(posedge aclk);
  burst_len : coverpoint awlen {
    bins single = {0};
    bins short  = {[1:3]};
    bins long   = {[4:15]}; }
  burst_typ : coverpoint awburst {
    bins fixed = {2'b00};
    bins incr  = {2'b01};
    bins wrap  = {2'b10}; }
  len_x_typ : cross burst_len, burst_typ;
endgroup

// Assertion: valid must hold until ready, no dropouts
property wr_handshake;
  @(posedge aclk) disable iff (!aresetn)
    awvalid && !awready |=> awvalid;
endproperty
assert property (wr_handshake);

Coverage points come from your specification, not from reading the RTL back to itself. A covergroup written from the code will happily report 100% on a design that does the wrong thing.

Methodology & tools

Plain testbenches, not a framework.

UVM is ASIC-scale methodology, and on most FPGA projects it costs more than it returns. You end up with a class hierarchy only a verification specialist can safely touch, on a team that does not have one. We write self-checking benches in plain SystemVerilog or VHDL instead, so your own engineers can read and extend them the day we hand over.

How we write them

SystemVerilog VHDL Self-checking Randomized stimulus Assertions cocotb

Simulators & tools

Questa / ModelSim VCS Xcelium Vivado Simulator Verilator

Beyond simulation

Where simulation alone will not get you there.

A
Formal property verification. Exhaustive proof of critical properties, useful for arbiters, FIFOs, and control logic where a random test might never hit the failing sequence.
B
Protocol VIP and compliance. Verification IP for AXI, AHB, APB, and Avalon so standard interfaces are checked against the specification rather than your reading of it.
C
Gate-level simulation. Post-synthesis and post-place-and-route runs with SDF timing, catching X-propagation and reset issues that RTL simulation hides.
D
Coverage-driven regression. Nightly runs with trend reporting, so a coverage regression fails a commit instead of surfacing the week before tape-out.

Why it matters

What coverage actually buys you.

Sign-off evidence

A coverage report traced to a verification plan is what a design review, a customer audit, or a safety process asks for. An assertion that it works is not.

Bugs found in simulation

Every defect caught here is one not debugged on hardware, where visibility is poor and each iteration costs a build.

Safe to change later

A regression suite at high coverage means the next engineer can refactor your RTL without quietly breaking it.

Honest numbers

The final stretch to 100% is mostly unreachable code. Documented, justified exclusions beat a padded number that falls apart under review.