02 / 08 · What we check

Consistency your whole team can rely on.

Style drift is how small teams end up with RTL that only the original author can safely touch. We check your project against common Verilog/VHDL house-style conventions and flag inconsistencies before they spread.

01
Naming conventions. Consistent prefixes/suffixes for clocks, resets, active-low signals, and registers.
02
Signal declarations. Explicit widths, consistent typing, and no implicit wire pitfalls.
03
Indentation & structure. Uniform formatting so diffs stay readable across contributors.
04
Comment quality. Comments that explain intent, not just restate the code.
05
File organization. One clear entity/module per file, with a predictable directory layout.

Sample findingCoding Standards

-- inconsistent naming across the same file
signal Data_valid   : std_logic;
signal rdy_n        : std_logic;
signal CLK_enable   : std_logic;
signal resetSignal  : std_logic;

Mixed naming case and reset polarity conventionsMinor

Inconsistent active-low naming is a common source of accidental polarity bugs when signals are reused elsewhere.

Why it matters

What this check protects you from.

Fewer silly bugs

Most polarity and typo bugs come from inconsistent naming, not logic errors.

Easier code review

A shared style means reviewers spend time on logic, not formatting nits.

Tool-friendly RTL

Consistent conventions play better with linters, CDC tools, and formal checkers.

All categories

Every review covers all 8.

Coding Standards is one of eight categories in every FPGAStudio review. Explore the rest below.

Resource Optimization

DSP & Fixed-Point

Detailed Report

Get your RTL reviewed by an expert.

No setup, no commitment. Just send us your project and we'll take it from there.

Request a Review →