04 / 08 · What we check

Every clock-domain crossing, checked for safe synchronization.

Metastability bugs are notoriously hard to reproduce in simulation and brutal to debug in silicon. We trace every signal that crosses a clock domain and confirm it's synchronized the way it should be.

01
Crossing inventory. A full list of every signal that moves between clock domains.
02
Synchronizer depth. Two-flop (or deeper) synchronizers where single-bit signals cross domains.
03
Multi-bit crossings. Gray-coding or handshake protection on buses crossing domains.
04
FIFO boundary checks. Correct use of async FIFOs at domain boundaries, not ad-hoc logic.
05
Reconvergence risk. Signals that cross back and forth between domains in ways that reintroduce risk.

Sample findingCDC Review

// clk_a domain
always @(posedge clk_a) data_valid_a <= trigger;

// clk_b domain: direct read, no synchronizer
always @(posedge clk_b) if (data_valid_a) latch_b <= data_a;

Single-bit signal crosses clk_a → clk_b with no synchronizerCritical

This is a direct metastability risk. A two-flop synchronizer (or handshake, for multi-bit data) is needed at this boundary.

Why it matters

What this check protects you from.

Silicon-only bugs

CDC failures rarely show up in RTL simulation and can take weeks to isolate on hardware.

Field reliability

Unsynchronized crossings cause intermittent failures that scale with unit volume.

Sign-off confidence

A clean CDC review is often a prerequisite before tape-out or production release.

All categories

Every review covers all 8.

CDC Review is one of eight categories in every FPGAStudio review. Explore the rest below.

Resource Optimization

DSP & Fixed-Point

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